make

http://linoxide.com/how-tos/linux-make-command-examples/
the make command accepts targets as command line arguments. These targets are usually specified in a file named ‘Makefile’, which also contains the associated action corresponding to the targets.
When the make command is executed for the very first time, it scans the Makefile to find the target (supplied to it) and then reads its dependencies. If these dependencies are targets themselves, it scans the Makefile for these targets and builds their dependencies (if any), and then builds them. Once the main dependencies are build, it then builds the main target
suppose you make change to only one source file and you execute the make command again, it will only compile the object files corresponding to that source file, and hence will save a lot of time in compiling the final executable.
Here are the details of the testing environment used for this article :
OS – Ubuntu 13.04
Shell – Bash 4.2.45
Application – GNU Make 3.81

http://www.cs.colby.edu/maxwell/courses/tutorials/maketutor/
example:
(varables)
IDIR =../include
CC=gcc
CFLAGS=-I$(IDIR)

ODIR=obj
LDIR =../lib

LIBS=-lm
DEPS = $(patsubst %,$(IDIR)/%,$(_DEPS))

_OBJ = hellomake.o hellofunc.o
OBJ = $(patsubst %,$(ODIR)/%,$(_OBJ))

(Target:dependencies)
$(ODIR)/%.o: %.c $(DEPS)
$(CC) -c -o $@ $< $(CFLAGS)

hellomake: $(OBJ)
gcc -o $@ $^ $(CFLAGS) $(LIBS)

.PHONY: clean

clean:
rm -f $(ODIR)/*.o *~ core $(INCDIR)/*~

$< is the first item in the dependencies list;
$@ is the left side of :
$^ is the right side of :
%.o any file ended with ‘.o’

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